Recently, in accordance with the increased density and the increased degree of integration of semiconductor integrated circuits (LSIs) used in electronic equipment, the number of electrode terminals of an LSI chip has been rapidly increased and the pitch therebetween has been rapidly reduced. In mounting such an LSI chip on a circuit board, flip-chip mounting is widely employed for reducing interconnect delay. Generally, in the flip-chip mounting, solder bumps are formed on electrode terminals of an LSI chip and the electrode terminals of the LSI chip are connected as a whole to connection terminals formed on a circuit board through the solder bumps.
However, in order to mount a next generation LSI including electrode terminals in the number exceeding 5,000 on a circuit board, it is necessary to form bumps correspondingly to a fine pitch of 100 μm or less, but it is difficult to cope with this fine pitch by the current solder bump forming technology. Also, since bumps in the large number corresponding to the number of electrode terminals should be formed, in order to reduce the cost, it is desired to attain high productivity by reducing mounting tact time per chip.
Similarly, in accordance with the increased number of electrode terminals, the arrangement of electrode terminals of semiconductor integrated circuits has been changed to area array arrangement from peripheral arrangement. Furthermore, in order to meet the demands for a higher density and a higher degree of integration, the semiconductor process is expected to be developed from 90 nm process to 65 nm or 45 nm process. As a result, the refinement of interconnects is further proceeded, and the capacitance between interconnects is increased. Therefore, problems of a rapid operation and a power consumption loss have become serious, and there are increasing demands for reducing the dielectric constant (i.e., attaining low-k) of an insulating film provided between interconnect layers. The low-k of such an insulating film can be realized by making the material for the insulating film porous, and therefore, such a film is poor in the mechanical strength and hence is an obstacle to thickness reduction of a semiconductor. Moreover, in the case where electrode terminals are formed in the area array arrangement, since the porous film has a problem of the strength due to its low-k, it is difficult to form bumps on the electrode terminals in the area array arrangement and to perform the flip-chip mounting itself. Accordingly, there is a demand for a small-load flip-chip mounting method suitably employed for a thin and high-density semiconductor coping with the future development of the semiconductor process.
As a technique for forming bumps, a plating method or a screen printing method is conventionally developed. Although the plating method is suitable for attaining a fine pitch, the process is complicated and is disadvantageous in the productivity. Alternatively, the screen printing method is good at productivity but is not suitable for attaining a fine pitch because a mask is used.
Under these circumstances, some techniques for forming solder bumps on electrodes of an LSI chip or a circuit board have been recently developed. These techniques are not only suitable for forming fine bumps but also good at productivity because bumps can be formed as a whole, and hence are regarded to be applicable to the mounting of a next generation LSI on a circuit board.
For example, in a technique disclosed in Patent Document 1, solder paste made of a mixture of a solder powder and a flux is solidly applied on a substrate on which electrodes have been formed, and the solder powder is melted by annealing the substrate, so as to selectively form solder bumps on the electrodes with high wettability.
Alternatively, in a technique disclosed in Patent Document 2, a paste composition including an organic acid lead salt and metal tin as principal components (chemical reaction depositing solder) is solidly applied on a substrate on which electrodes have been formed, and a substitution reaction between Pb and Sn is caused by annealing the substrate, so as to selectively deposit Pb/Sn alloy on the electrodes of the substrate.
However, in both of the techniques disclosed in Patent Documents 1 and 2, the paste composition is supplied onto the substrate through application, and hence, variation in thickness and concentration is locally caused. Therefore, the amount of depositing solder is different among the electrodes, and hence, the bumps cannot be formed in a uniform height. Also, in these methods, since the paste composition is supplied by the application onto the irregular surface of the circuit board where the electrodes have been formed, a sufficient amount of solder cannot be supplied onto the electrodes corresponding to convex portions, and therefore, it is difficult to attain a desired height of bumps necessary for the flip-chip mounting.
In the flip-chip mounting employing the conventional bump formation method, after mounting a semiconductor chip on a circuit board where bumps have been formed, it is necessary to further perform a procedure for injecting a resin designated as an underfill resin into a space between the semiconductor chip and the circuit board for fixing the semiconductor chip on the circuit board.
Therefore, as a method for simultaneously obtaining electric connection between opposing electrode terminals of a semiconductor chip and a circuit board and fixing the semiconductor chip on the circuit board, a flip-chip mounting technique using an isotropic conducting material (see, for example, Patent Document 3) has been developed. In this method, a thermosetting resin including conducting particles is supplied between a circuit board and a semiconductor chip and a pressure is applied to the semiconductor chip at the same time as the thermosetting resin is annealed. Thus, the electric connection between the electrode terminals of the semiconductor chip and the circuit board and the fixation of the semiconductor chip on the circuit board can be simultaneously realized.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2000-94179    Patent Document 2: Japanese Laid-Open Patent Publication No. 1-157796    Patent Document 3: Japanese Laid-Open Patent Publication No. 2000-332055